The present invention generally relates to data processing systems and more particularly to arithmetic logic which is used therein.
When performing arithmetic operations in a data processing system, the operands being operated upon are in a binary form or in binary coded decimal form. For example, the number 13 in binary form would be expressed in binary ones and zeros as 1101, whereas in binary coded decimal form it would be expressed as 0001 0011. It can be seen that for the binary coded decimal number, the least significant number of the number 13, i.e., the number 3, is expressed in the right most four ones and zeros and the most significant number 1 of the number 13 is expressed in the left most combination of ones and zeros. In order to minimize cost, such data processing systems sometimes include only a single arithmetic unit for performing operations on such operands. In the case where a binary arithmetic logic unit is utilized, binary operands are operated upon in a conventional manner. However, for the case where binary coded decimal numbers must be operated upon by use of a binary arithmetic logic unit, the result produced by such binary arithmetic logic must be corrected in order to produce the correct result. This has been accomplished in the prior art by use of the well-known excess six correction technique. One implementation of such excess six correction technique is shown in block diagram form in FIG. 6 hereof. It can be seen from further reading herein, that such excess six correction technique of the prior art requires logic for one operand wherein a conditional add operation takes place, and second logic coupled to the output of the binary arithmetic logic unit wherein a conditional subtract operation may take place. It has been found that the use of such logic in such implementation is costly in that increased logic is required. In addition, such logic requires additional physical space which is not desirable, particularly as processors become more and more integrated on, for example, a single circuit board.
It is, accordingly, a primary object of the present invention to provide a data processing system having an improved apparatus for correcting the result produced by a binary arithmetic logic unit when operating upon two operands in binary coded decimal form.